1. Field of the Invention
The present invention relates to a battery state monitoring circuit for monitoring a battery state, and a battery device provided with a plurality of the battery state monitoring circuits.
2. Description of the Related Art
FIG. 2 illustrates a circuit diagram of a conventional battery device including battery state monitoring circuits.
The battery device includes n batteries BT1 to BTn that are connected in series, n switches (cell balance switch circuits) SW1 to SWn that are respectively connected in parallel with the batteries BT1 to BTn, n battery state monitoring circuits BMF1 to BMFn that are individually provided in correspondence with the batteries BT1 to BTn, a first transistor (charging P-channel transistor) 10, a second transistor (discharging P-channel transistor) 11, a first resistive element (first bias resistive element) 20, a second resistive element (second bias resistive element) 21, an overcurrent detection circuit X, a first external terminal 30, and a second external terminal 31.
The battery state monitoring circuit BMF1 includes an overcharge detection circuit A1, a first NOR circuit B1, a first output transistor C1, a first inverter D1, a second inverter E1, a first current source F1, an overdischarge detection circuit G1, a second NOR circuit H1, a second output transistor I1, a third inverter J1, a fourth inverter K1, a second current source L1, a cell balance circuit M1, an overdischarge cell balance circuit XC1, a first OR circuit XD1, a first voltage monitoring terminal PA1, a second voltage monitoring terminal PB1, a first transmitting terminal PC1, a second transmitting terminal PD1, a first receiving terminal PE1, a second receiving terminal PF1, and a control terminal PG1. The battery state monitoring circuit BMF1 including the above-mentioned components is formed as a one-chip IC (semiconductor device). Note that, of the above-mentioned components, the first NOR circuit B1, the first output transistor C1, the first inverter D1, the second inverter E1, and the first current source F1 together form an overcharge information communication circuit. Further, the second NOR circuit H1, the second output transistor I1, the third inverter J1, the fourth inverter K1, and the second current source L1 together form an overdischarge information communication circuit.
The overdischarge cell balance circuit XC1 includes a fifth inverter XA1 and a first AND circuit XB1. The first OR circuit XD1 receives respective outputs of the overdischarge cell balance circuit XC1 and the cell balance circuit M1, and outputs a control signal to the switch SW1 via the control terminal PG1.
The other battery state monitoring circuits BMF2 to BMFn each include the same components as those of the battery state monitoring circuit BMF1, and hence are illustrated similarly, except for different reference symbols. For example, the overcharge detection circuit included in the battery state monitoring circuit BMF2 is denoted by reference symbol A2, and the overcharge detection circuit included in the battery state monitoring circuit BMFn is denoted by reference symbol An. The same holds true for the other components.
The battery state monitoring circuit BMFn is not connected with a battery state monitoring circuit that outputs signals to be transmitted to the first receiving terminal PEn and the second receiving terminal PFn. Therefore, the first receiving terminal PEn for receiving an overcharge detection signal is pulled down.
The overcurrent detection circuit X is provided on a discharge path between the first external terminal 30 and the second external terminal 31. An output terminal of the overcurrent detection circuit X is connected to the second receiving terminal PFn of the battery state monitoring circuit BMFn. The overcurrent detection circuit X is configured to detect an overcurrent based on voltage, and hence includes, for example, an element for converting current into voltage, such as a resistive element, and a comparator circuit for detecting the voltage.
The battery device illustrated in FIG. 2 performs discharge or charge when a load or a charger is connected between the first external terminal 30 and the second external terminal 31.
In a normal state, that is, in a case where all of voltages of the batteries BT1 to BTn fall within a voltage range lower than an overcharge voltage and equal to or higher than an overdischarge voltage, the overcharge detection circuit A1 included in the battery state monitoring circuit BMF1 outputs the overcharge detection signal of Low to the first NOR circuit B1.
On this occasion, the first output transistor C2 included in the battery state monitoring circuit BMF2 has been turned ON (the reason is described later), and hence an input terminal of the second inverter E1 included in the battery state monitoring circuit BMF1 becomes Low. Therefore, the first inverter D1 outputs an output signal of Low to the first NOR circuit B1. Because the first NOR circuit B1 receives the overcharge detection signal of Low and the output signal of Low of the first inverter D1 as inputs, the first NOR circuit B1 outputs a NOR signal of High to a gate terminal of the first output transistor C1. Then, the first output transistor C1 is turned ON, and the first transmitting terminal PC1 becomes Low. As a result, the first transistor 10 is turned ON.
The reason why the first output transistor C2 included in the battery state monitoring circuit BMF2 has been turned ON is described below. The first receiving terminal PEn of the battery state monitoring circuit BMFn provided at the lowermost stage is connected with a negative terminal of the battery BTn, and hence the input terminal of the second inverter En is continuously kept at Low. Therefore, the first inverter Dn continuously outputs the output signal of Low to the first NOR circuit Bn, and the overcharge detection circuit An outputs the overcharge detection signal of Low to the first NOR circuit Bn. Accordingly, the first NOR circuit Bn outputs the NOR signal of High to the gate terminal of the first output transistor Cn, and then the first output transistor Cn included in the battery state monitoring circuit BMFn is turned ON.
Because the first output transistor Cn is turned ON, the input terminal of the second inverter En-1 included in the battery state monitoring circuit BMFn-1 becomes Low. Therefore, the first inverter Dn-1 outputs the output signal of Low to the first NOR circuit Bn-1. Similarly, the overcharge detection circuit An-1 outputs the overcharge detection signal of Low to the first NOR circuit Bn-1. Accordingly, the first NOR circuit Bn-1 outputs the NOR signal of High to the gate terminal of the first output transistor Cn-1. Then, the first output transistor Cn-1 included in the battery state monitoring circuit BMFn-1 is turned ON.
The operations described above are repeatedly performed in a battery state monitoring circuit provided on an upper stage side and a battery state monitoring circuit provided on a lower stage side, and the first output transistor C2 included in the battery state monitoring circuit BMF2 is eventually turned ON.
On the other hand, in the normal state described above, the overdischarge detection circuit G1 included in the battery state monitoring circuit BMF1 outputs an overdischarge detection signal of Low to the second NOR circuit H1. On this occasion, the second output transistor I2 included in the battery state monitoring circuit BMF2 has also been turned ON, and hence the input terminal of the fourth inverter K1 included in the battery state monitoring circuit BMF1 becomes Low. Therefore, the third inverter J1 outputs an output signal of Low to the second NOR circuit H1. Because the second NOR circuit H1 receives the overdischarge detection signal of Low and the output signal of Low of the third inverter J1 as inputs, the second NOR circuit H1 outputs a NOR signal of High to a gate terminal of the second output transistor I1. Then, the second output transistor I1 is turned ON, and the second transmitting terminal PD1 becomes Low. As a result, the second transistor 11 is turned ON.
As described above, in the normal state, because the first transistor 10 and the second transistor 11 are turned ON, the battery device becomes a chargeable and dischargeable state.
Next, description is given of an overdischarged state, that is, a case where the load is connected between the first external terminal 30 and the second external terminal 31 to thereby discharge the batteries BT1 to BTn, and at least one voltage of the batteries BT1 to BTn becomes lower than the overdischarge voltage. Note that the following description is given under the assumption that the voltage of the battery BT1 is higher than the overdischarge voltage while the voltage of the battery BT2 becomes lower than the overdischarge voltage.
In this case, the overdischarge detection circuit G2 included in the battery state monitoring circuit BMF2 outputs the overdischarge detection signal of High to the second NOR circuit H2. Then, the second NOR circuit H2 outputs the NOR signal of Low to the gate terminal of the second output transistor I2. Accordingly, the second output transistor I2 is turned OFF.
The input terminal of the fourth inverter K1 is pulled up to High by the second current source L1, and the third inverter J1 outputs the output signal of High to the second NOR circuit H1. Then, the second NOR circuit H1 outputs the NOR signal of Low to the gate terminal of the second output transistor I1. Accordingly, the second output transistor I1 is turned OFF.
When the second output transistor I1 is turned OFF as described above, a gate of the second transistor 11 becomes High due to the second resistive element 21, and as a result, the second transistor 11 is turned OFF, to thereby inhibit the discharge to the load.
On the other hand, because the voltage of the battery BT1 is higher than the overdischarge voltage, the overdischarge detection circuit G1 outputs the overdischarge detection signal of Low. Therefore, the first AND circuit XB1 receives a signal of High from the fifth inverter XA1 and the signal of High from the third inverter J1 as inputs, and hence the first AND circuit XB1 outputs a signal of High, that is, an overdischarge cell balance signal to the first OR circuit XD1.
In this case, when receiving the overdischarge cell balance signal, the first OR circuit XD1 turns ON the switch SW1 via the control terminal PG1 so that the battery BT1 may be discharged via the switch SW1. When the discharge proceeds until the voltage of the battery BT1 reaches the overdischarge voltage, the overdischarge detection circuit G1 outputs the overdischarge detection signal of High. As a result, the first OR circuit XD1 turns OFF the switch SW1 via the control terminal PG1 so that the discharge may be stopped.
Through the operations described above, both the voltages of the battery BT1 and the battery BT2 become approximate to the overdischarge voltage. The cell balance is obtained as described above so that the battery device may be allowed to operate for a longer time.
The overcurrent detection circuit X detects an excessive discharge current (hereinafter, referred to as “overcurrent”) flowing into the load connected between the first external terminal 30 and the second external terminal 31 of the battery device. In a state where the overcurrent is not detected, the overcurrent detection circuit X pulls down the second receiving terminal PFn to Low. If the overcurrent occurs, the overcurrent detection circuit X stops pulling down the second receiving terminal PFn, to thereby transmit overcurrent detection information to the battery state monitoring circuit BMFn.
Then, the second current source Ln pulls up the input terminal of the fourth inverter Kn so that the signal may be transmitted to the battery state monitoring circuit BMFn-1 provided at the subsequent stage via the overdischarge information communication circuit included in the battery state monitoring circuit BMFn. Finally, the battery state monitoring circuit BMF1 inhibits the discharge to the load (see, for example, Japanese Patent Application No. 2007-178834).
However, in the example of FIG. 2, there is a problem that the discharge of the respective batteries may proceed because the cell balance switch circuits SW1 to SWn for the batteries are turned ON at the same timing when the discharge to the load is inhibited upon the detection of the overcurrent.
Specifically, when the battery state monitoring circuits BMF1 to BMFn receive the signals via the corresponding second receiving terminals PF1 to PFn, the battery state monitoring circuit cannot discriminate which of the overdischarge detection and the overcurrent detection the signal results from. Therefore, even when the discharge needs to be stopped because of the overcurrent detection, the battery state monitoring circuits may each determine that any one of the battery state monitoring circuits has detected the overdischarge. Then, the overdischarge cell balance signal is output to turn ON the cell balance switch circuit. In this case, all the voltages of the batteries decrease to as low as the overdischarge voltage after the overcurrent has been detected. Therefore, the battery device cannot be used until the voltages of the batteries are charged to be recovered, resulting in significantly worse usability.